Because the recent semiconductor integrated circuits become more and more complicated and high level, recent semiconductor test systems for testing such integrated circuits also have become more and more complicated and large scale. For example, the number of pins of a recent semiconductor device under test (hereinafter sometimes referred to as "DUT") extends to as many as 1,000, which requires that a semiconductor test system (test system) for testing such a DUT be equipped 1,000 or more test channels (hereafter may also be referred to as "tester pins"). Each tester channel includes a pattern generator, a timing generator, a test waveform formatter, as well as a driver and a comparator to independently supply a desired test pattern to a corresponding pin of the DUT to evaluate the performance at the pin of the DUT.
FIG. 1 is a schematic block diagram showing an example of such a test system. In this example, the test system is illustrated by a combination of basic functional blocks, and thus, each test channel (tester pin) noted above is not shown. In FIG. 1, the test system is comprised of a work station 12, a test controller 14, a test unit 15, and a test head 16 for testing a device under test 18. The work station 12 functions as a user interface and operates under an operating system such as UNIX. The work station 12 may be connected to a network 11 to establish a test system network having a plurality of test systems.
The tester controller 14 is an exclusive processor provided in the test system to control various operations of the test system. The test unit 15 is to provide a test pattern to the device under test and is formed with a pattern generator, a timing generator, a wave formatter and the like. The test head 16 is comprised of a driver for providing a test pattern to the device under test 18 with a predetermined amplitude and threw rate, and a comparator for detecting an output signal level of the device under test 18 and comparing the detected signal with the expected value data. In the above noted configuration of the test system, the test unit 15 and the test head 16 are provided for each tester pin (test channel), the number of the tester pins is the same or greater than the maximum number of pins of the device to be tested.
As in the foregoing, because the test system has a circuit configuration of complicated and large scale, an overall test system of today is a very large system having a large number of components. As a consequence, a test system cannot be completely immune to occurrences of failures and must be prepared to any defects. For example, when a defect is discovered in a certain tester pin of the test system when using the test system or by running a self diagnostic test, a maintenance process will be conducted in which the defective tester pin may be replaced with an interchangeable tester pin (supplemental tester pin).
In such a replacement of components in the test system, however, it is not preferable if the user of the test system must modify the test program for the test system or must prepare a new test program reflecting the changes in the test system, or must keep the data regarding the hardware structural changes in the test system, because it is too burdensome to the user. Therefore, there is a need that the user can use the test system in the same manner as before without worrying about any changes resulted from the maintenance work.